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? semiconductor components industries, llc, 2009 july, 2009 ? rev. 0 1 publication order number: dap018/d customer specific device from on semiconductor pwm current-mode controller for high-power universal off-line supplies housed in a so ? 14 package, the dap018x represents an enhanced version of the currently available speedking controller, the dap011. with an internal structure operating at a fixed 65 khz or 100 khz frequency, the controller directly connects to the high ? voltage rail for a lossless and clean startup sequence. current ? mode control also provides an excellent input audio ? susceptibility and inherent pulse ? by ? pulse control. internal ramp compensation easily prevents sub ? harmonic oscillations from taking place in continuous conduction mode designs. on top of these features, the device takes advantage of the auxiliary winding negative swing to let the user adjust the maximum power the converter can deliver in high line conditions (opp). when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically freezes the peak current and reduces its switching frequency down to 25 khz. at this point, if further output power reduction occurs, the controller enters skip ? cycle. the dap018x features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses while the device enters a safe burst mode, trying to re ? start. once the fault has gone, the device auto ? recovers. by implementing a timer to acknowledge a fault condition, independently from the auxiliary supply, the designer?s task is eased when stringent fault mode conditions need to be met. a dedicated input helps triggering a latch ? off circuitry which permanently disables output pulses, for instance to implement an over voltage protection (ovp). a separate input accepts a direct ntc connection to ground for a simple and efficient over temperature protection (otp). features ? fixed ? frequency 65 khz (a and b versions) or 100 khz (c and d versions) current ? mode control operation ? internal and adjustable over power protection (opp) circuit ? frequency foldback down to 25 khz and skip ? cycle in light load conditions ? reduced internal bias currents for improved standby performance ? adjustable brown ? out protection (b and d versions) ? internal ramp compensation ? internal fixed 5 ms soft ? start ? adjustable frequency jittering for better emi signature ? auto ? recovery internal output short ? circuit protection for a, b, c and d versions. f is latched ? adjustable timer for improved short ? circuit protection ? otp and ovp inputs for improved robustness ? +500 ma / ? 800 ma peak current capability ? up to 28 v v cc operation ? improved creepage distance between high ? voltage and adjacent pin ? extremely low no ? load standby power ? this is a pb ? free device ? this device uses halogen ? free molding compound typical applications ? high power ac ? dc converters for tvs, set ? top boxes etc. ? offline adapters for notebooks marking diagram pin connections soic ? 14 d suffix case 751a (top view) 1 14 dap018x awlywwg 1 14 x = device version a = assembly location wl = wafer lot y = year ww = work week g = pb ? free package ctimer ovp opp jittering fold fb cs 1 2 3 4 5 6 7 14 13 12 11 10 9 8 hv nc otp bo(b&d) v cc drv gnd ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. see detailed ordering and shipping information in the package dimensions se ction on page 3 of this data sheet. ordering information dap018a/b/c/d/f
dap018a/b/c/d/f http://onsemi.com 2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 *see note ovp freq. jitter foldback adj. + vbulk nc / a&c v out + gnd ramp gnd timer delay *this resistor prevents from negatively biasing the hv pin (14) at power ? off. typical value is 4.7 k . figure 1. typical application example otp + roppl roppu pin no. pin name function pin description 1 opp adjust the over power protection a resistive divider from the auxiliary winding to this pin sets the opp compensation level. 2 ovp input voltage to latch comparator this pin offers an over ? voltage protection input. 3 ctimer timer wiring a capacitor to ground helps selecting the timer duration. 4 jitter frequency jittering speed this pin offers a way to adjust the frequency modulation pace. 5 foldback / skip frequency foldback / skip cycle adjustment by connecting a resistor to ground, it becomes possible to re- duce the level at which frequency foldback occurs. 6 fb feedback pin hooking an optocoupler collector to this pin will allow regulation. 7 cs current sense + ramp compensation this pin monitors the primary peak current but also offers a means to introduce ramp compensation. 8 gnd ? the controller ground. 9 drv driver output the driver?s output to an external mosfet gate. 10 v cc supplies the controller this pin is connected to an external auxiliary voltage. 11 bo brown ? out, b and d versions for b and d versions, this pin offers a brown ? out input. 12 otp ntc connection this pin connects to a pulldown ntc resistor for over temperat- ure protection (otp). 13 nc ? non ? connected for improved creepage. 14 hv high ? voltage input connected to the bulk capacitor, this pin powers the internal current source to deliver a startup current.
dap018a/b/c/d/f http://onsemi.com 3 ordering information delta device on semiconductor device frequency brown ? out short ? circuit package shipping ? dap018adr2g scy99079adr2g 65 khz no auto ? recovery soic ? 14 (pb ? free) 2500 / tape & reel dap018bdr2g scy99079bdr2g 65 khz yes auto ? recovery soic ? 14 (pb ? free) 2500 / tape & reel dap018cdr2g scy99079cdr2g 100 khz no auto ? recovery soic ? 14 (pb ? free) 2500 / tape & reel DAP018Ddr2g scy99079ddr2g 100 khz yes auto ? recovery soic ? 14 (pb ? free) 2500 / tape & reel dap018fdr2g scy99079fdr2g 65 khz yes latched soic ? 14 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
dap018a/b/c/d/f http://onsemi.com 4 1 2 latch + - s q q r + v latch + - fault v cc and logic management 5 v on v cc reset power on reset v ccon v cc(min) v cclatch + + - ic1 hv 14 ipflag fault 13 12 11 bo 10 v cc 9 drv v dd 65/100 khz clock s q q r + - 5 ms ss ipflag rramp 6 fb v dd rfb 7 cs leb 8 gnd + - v skip 5 fold i fold v dd + 2.icjit + - icjit v dd frequency modulation + v timfault ipflag power on reset v dd i tim 4 jitter 3 timer figure 2. internal circuit architecture v fold /4.2 /4.2 - + + frequency foldback + - + opp soft ? start ended? yes = 1, no = 0 votp iotp from fault in ocp latched versions 20 s time constant 5 v reset bo release (b & d) skip standby? bias reduction the soft ? start is activated during: ? the startup sequence ? the auto ? recovery burst mode ? a brown ? out release (b & d) vfb/4.2 > vset > vfold/4.2 vopp vlimit + vopp + vlimit clamp bo (dble hiccup reset) + - vbo + ibo b and d versions turned off when bo ok v dd vfold + bo ok 20 s time constant nc otp
dap018a/b/c/d/f http://onsemi.com 5 maximum ratings table symbol rating value unit v ccmax maximum power supply voltage, v cc pin, continuous voltage ? 0.3 to 28 v i ccmax maximum current for v cc pin 30 ma maximum voltage on low power pins (except pins 9, 10 and 14) ? 0.3 to 10 v iopp maximum injected negative current into the opp pin (pin 1) ? 2 ma r j ? a thermal resistance junction ? to ? air 120 c/w tj max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, human body model (all pins except hv) 2 kv esd capability, machine model 180 v maximum voltage on pin 14 (hv) ? 0.3 to 500 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. notes:this device(s) contains esd protection and exceeds the following tests: human body model 2000v per jedec standard jesd22 ? a114e machine model 200v per jedec standard jesd22 ? a115 ? a this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78 except pin 12. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 25 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit supply section v cc on v cc increasing level at which the current source turns ? off 10 14 15 16 v v cc (min) v cc level below which output pulses are stopped 10 8 9 10 v v cc latch v cc decreasing level at which the latch ? off phase ends 10 7.2 7.5 8.0 v v cc reset internal latch reset level 10 5 v resethyst minimum voltage difference between v cc latch and v cc reset, t j > 0 c ? 0.8 v v cc tsd v cc voltage when the tsd is activated (note 2) ? 6.5 7.1 v i cc1 internal ic consumption, no output load on pin 9 10 1.9 ma i cc1light icc1 for a feedback voltage equal to vfold (internal bias reduction) 10 1.5 ma i cc2 internal ic consumption, 1 nf output load on pin 9 10 2.7 ma i cc3 internal ic consumption, latch ? off phase 10 0.6 ma i tsd current consumption in tsd mode ? 400 a internal start ? up current source ? high ? voltage pin biased to 60 vdc. symbol rating pin min typ max unit ic2 high ? voltage current source, v cc = 10 v 14 3 6 9 ma ic1 high ? voltage current source, v cc = 0, t j = 25 c 14 150 650 1200 a v th v cc transition level for ic1 to ic2 toggling point 14 0.9 v i leak leakage current for the high voltage source, vpin 14 = 500 vdc, v cc = 12 v, t j > 0 c 14 1 15 30 a drive output symbol rating pin min typ max unit t r output voltage rise ? time @ c l = 1 nf, 10 ? 90% of a 12 v output signal 9 ? 40 ? ns 1. see characterization table for linearity over negative bias voltage. 2. guaranteed by design. 3. the otp parameters are selected to cope with a ttc03 ? 474 which offers a resistance of 8.8 k when heated to a temperature of 110 c. 4. the brown ? out circuitry is disabled on versions a & c and operates on versions b & d.
dap018a/b/c/d/f http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 25 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) drive output symbol unit max typ min pin rating t f output voltage fall ? time @ c l = 1 nf, 10 ? 90% of a 12 v output signal 9 ? 25 ? ns isource source current capability at v drv = 10.5 v 9 ? 500 ? ma isink sink current capability at v drv = 0 v 9 ? 800 ? ma v drvlow drv pin level at v cc close to v cc(min) with a 33 k resistor to gnd 9 7.6 ? ? v v drvhigh drv pin level at v cc = 28 v 9 10 15 17 v current comparator symbol rating pin min typ max unit i ib input bias current @ 0.8 v input level on pin 7 7 0.02 a v limit maximum internal current setpoint ? pin1 grounded 7 0.76 0.8 0.84 v t del propagation delay from current detection to gate off ? state 7 100 150 ns t leb leading edge blanking duration 7 140 ns tss internal soft ? start duration activated upon startup, auto ? recovery and bo release for versions b & d, pin 1 grounded. ? 5 ms ioppo setpoint decrease for pin 1 biased to ?300 mv (note 1) 1 37.5 % ioopv voltage setpoint for pin 1 biased to ? 300 mv (note 1) 1 0.46 0.5 0.54 v iopps setpoint decrease for pin 1grounded 1 0 % internal oscillator symbol rating pin min typ max unit f osc oscillation frequency (65 khz version, a & b) ? 60 65 70 khz f osc oscillation frequency (100 khz version, c & d) ? 92 100 108 khz d max maximum duty ? cycle ? 76 80 84 % f jitter frequency jittering in percentage of f osc ? 5 % f swing swing frequency with a 22 nf capacitor to pin 4 4 300 hz icjit jittering modulator charging current 4 18 a vcjitp jittering capacitor peak voltage 4 2.2 v vcjitv jittering capacitor valley voltage 4 0.8 v feedback section symbol rating pin min typ max unit r up internal pull ? up resistor 6 20 k r fb equivalent resistor on fb pin 16 k i ratio pin 6 to current setpoint division ratio ? 4.2 k frequency foldback symbol rating pin min typ max unit i fold internal foldback reference current 5 8.5 10 11.5 a v fold frequency folback level with a 100 k resistor to ground 5 1 v i skip skip current in percentage of the maximum excursion, for v fold = 1 v 30 % f trans transition frequency below which skip ? cycle occurs for t j = 25 c ? 21 25 29 khz v skip skip ? cycle level voltage on the feedback pin 6 320 mv 1. see characterization table for linearity over negative bias voltage. 2. guaranteed by design. 3. the otp parameters are selected to cope with a ttc03 ? 474 which offers a resistance of 8.8 k when heated to a temperature of 110 c. 4. the brown ? out circuitry is disabled on versions a & c and operates on versions b & d.
dap018a/b/c/d/f http://onsemi.com 7 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 25 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) internal ramp compensation symbol rating pin min typ max unit v ramp internal ramp level @ 25 c (note 2) 7 3.0 v r ramp internal ramp resistance to cs pin (note 2) 7 20 k protections symbol rating pin min typ max unit v latch latching level input 2 2.85 3 3.25 v t latch ? del delay before latch confirmation ? 20 s v tim fault timer level completion 3 4.3 v i tim timer capacitor charging current 3 12 a timerl timer length, ctimer = 0.22 f typical 3 100 ms v bo brown ? out level ? b & d versions 11 0.95 1 1.05 v i bo hysteresis current, vpin 11 < v bo ? b & d versions, t j = 25 c 11 9 10 11 a i bo hysteresis current, vpin 11 < v bo ? b & d versions, ? 25 c < t j < 25 c 11 8.6 10 11 a i bo bias brown ? out input bias current ? b & d versions 11 0.02 a t bo ? del delay before brown ? out confirmation ? 20 s i otp over temperature shutdown current (note 3) 12 101 113 124 a v otp over temperature latching voltage (note 3) 12 0.95 1 1.05 v tsd temperature shutdown ? 140 c tsd_hys temperature shutdown hysteresis ? 40 c 1. see characterization table for linearity over negative bias voltage. 2. guaranteed by design. 3. the otp parameters are selected to cope with a ttc03 ? 474 which offers a resistance of 8.8 k when heated to a temperature of 110 c. 4. the brown ? out circuitry is disabled on versions a & c and operates on versions b & d.
dap018a/b/c/d/f http://onsemi.com 8 figure 3. v cc_latch vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 v cc_latch (v) 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 figure 4. i cc2 vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 i cc (ma) 0 5 10 15 20 25 30 35 ? 40 ? 15 ? 10 35 60 85 110 135 figure 5. high ? voltage leakage curren vs. temperature temperature ( c) i leak ( a) 0 20 40 60 80 100 120 140 160 figure 6. propagation delay vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 t del (ns) 6.8 7 7.2 7.4 7.6 7.8 8 3.1 3.6 4.1 4.6 5.1 figure 7. fault timer level vs. temperature temperature ( c) v timfault (v) ? 40 ? 15 ? 10 35 60 85 110 135 0.75 0.76 0.77 0.78 0.79 0.8 0.81 0.82 0.83 0.84 0.85 v limit (v) temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 figure 8. current sense internal setpoint vs. temperature
dap018a/b/c/d/f http://onsemi.com 9 100 105 110 115 120 125 i otp ( a) figure 9. otp current vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 57 59 61 63 65 67 69 71 73 ? 40 ? 15 ? 10 35 60 85 110 135 figure 10. oscillator frequency vs. temperature temperature ( c) fosc (khz) 75 76 77 78 79 80 81 82 83 84 85 d max (%) figure 11. maximum duty ? cycle vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 13.9 14.4 14.9 15.4 15.9 ? 40 ? 15 ? 10 35 60 85 110 135 figure 12. v cc(on) voltage vs temperature temperature ( c) v cc(on) (v) 7.9 8.4 8.9 9.4 9.9 v cc(min) (v) figure 13. v cc(min) voltage vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 4.9 5.4 5.9 6.4 6.9 7.4 7.9 v cc(latch) (v) figure 14. v cc(latch) vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135
dap018a/b/c/d/f http://onsemi.com 10 2.9 3.4 3.9 4.4 4.9 5.4 5.9 v cc(reset) (v) figure 15. v cc(reset) vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 0.9 1.4 1.9 2.4 2.9 3.4 3.9 4.4 4.9 ? 40 ? 15 ? 10 35 60 85 110 135 figure 16. v cc(latch) ? vcc hyst vs temperature temperature ( c) reset hyst (v) 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 i cc1 (ma) figure 17. i cc1 vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 4.6 5.1 figure 18. i cc1(light) vs temperature temperature ( c) i cc1(light) (ma) ? 40 ? 15 ? 10 35 60 85 110 135 0.04 0.14 0.24 0.34 0.44 0.54 i cc3 (ma) figure 19. i cc3 vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 0 1 2 3 4 5 v th (v) figure 20. threshold voltage vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135
dap018a/b/c/d/f http://onsemi.com 11 6 8 10 12 14 16 18 v drv(low) (v) figure 21. v drv(low) vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 10 11 12 13 14 15 16 17 18 figure 22. drive voltage v drv(high) vs temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 v dr(high) (v) 140 190 240 290 340 ? 40 ? 15 ? 10 35 60 85 110 135 figure 23. skip level vs. temperature temperature ( c) v lskip (mv) 1.4 1.9 2.4 2.9 3.4 figure 24. ramp level vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 v ramp (v) 9 11 13 15 17 19 21 figure 25. ramp resistor value vs. temperature r ramp (k ) ? 40 ? 15 ? 10 35 60 85 110 135 temperature ( c) 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 ? 40 ? 15 ? 10 35 60 85 110 135 figure 26. latching level vs. temperature temperature ( c) v latch (v)
dap018a/b/c/d/f http://onsemi.com 12 0.94 0.96 0.98 1 1.02 1.04 1.06 v bo (v) temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 8.9 9.4 9.9 10.4 10.9 temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 ibo a) 0.94 0.96 0.98 1 1.02 1.04 1.06 v otp (v) figure 27. v otp voltage vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 figure 28. brown ? out level vs. temperature figure 29. brown ? out hysteresis current vs. temperature 2.9 3.9 4.9 5.9 6.9 7.9 8.9 ic2 (ma) figure 30. ic2 startup current vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135 0 200 400 600 800 1000 1200 1400 1600 1800 ic1 ( a) figure 31. ic1 startup current vs. temperature temperature ( c) ? 40 ? 15 ? 10 35 60 85 110 135
dap018a/b/c/d/f http://onsemi.com 13 application information introduction speedking ii implements a standard current mode architecture where the switch ? off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part ? count is the key parameter, particularly in low ? cost ac ? dc adapters, open ? frame power supplies etc. thanks to its high ? voltage technology, the dap ? 018x incorporates all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as an adjustable emi jittering and a fault timer... ? current ? mode operation with internal ramp compensation: implementing peak current mode control, the dap ? 018x offers an internal ramp compensation signal that can easily by summed up to the sensed current. subharmonic oscillations can thus be fought via the inclusion of a simple resistor in series with the current ? sense information. ? internal opp: by routing a portion of the negative voltage present during the on ? time on the auxiliary winding to the dedicated opp pin, the user has a simple and non ? dissipative option to alter the maximum peak current setpoint as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. if the pin receives a negative voltage down to ?300 mv, then a peak current reduction down to 40% typical can be achieved. for an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 v. ? internal high ? voltage startup switch: reaching a low no ? load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. thanks to an internal logic, the controller disables the high ? voltage current source after startup which no longer hampers the consumption in no ? load situations. ? emi jittering: a dedicated pin offers the ability to vary the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to avoid modulation conflicts, the jittering will be disabled as soon as the controller enters frequency folback (light load conditions). ? frequency foldback capability: a continuous flow of pulses in not compatible with no ? load standby power requirements. the controller observes the feedback pin and when it reaches a level determined by pin 5, the peak current freezes. the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. it can decrease down to 26 khz (typical). at this point, if the power continues to drop, the controller enters classical skip ? cycle mode at a peak current set by pin 5 level. the point at which the foldback occurs can be adjusted to any level, we recommend to put it in the vicinity of 1 v or slightly above. ? bias reduction: the controller detects that standby mode is entered by monitoring the feedback pin level. when this occurs, the circuit significantly reduces its bias current by shutting down un ? necessary blocks. this improves the standby power further. ? brown ? out: versions b & d include a brown ? out (bo) detector. when the voltage sensed on this pin is below the bo level, the controller does not operate. when the voltage reaches the threshold, the controller pulses and open the internal hysteresis current source. by connecting a divider network between the bulk voltage and the bo pin, the designer has the flexibility to adjust the turn ? on and turn ? off levels. for versions a & c, the brown ? out circuitry is disabled and pin 11 is not internally connected. ? internal soft ? start: a soft ? start precludes the main power switch from being stressed upon start ? up. in this controller, the soft ? start is internally fixed to 5 ms. the soft ? start is activated when a) a new startup sequence occurs ? fresh startup or during an auto ? recovery hiccup b) when the controller recovers from a brown ? out condition (b & d versions). ? ovp input: the speedking ii includes a latch input that can be used to sense an overvoltage condition on the adapter. if this pin is brought higher than the internal reference voltage v latch , then the circuit permanently latches off. the v cc pin swings up and down, keeping the controller latched. the latch reset occurs when a) the user disconnects the adapter from the mains and lets the v cc falls below the v ccreset value b) for versions b & d, if the internal bo circuitry senses a bulk / mains reset, then the controller is also reset. in this case, if the controller is within a hiccup cycle: the hiccup cycle is immediately reset and driving pulses only re ? appear on the output when v cc reaches v cc(on) . ? otp input: the controller incorporates an over temperature protection circuitry (otp) which allows the direct connection of a negative temperature coefficient (ntc) sensor from pin 12 to gnd. when the temperature increases, the ntc resistor falls down. when the ntc reaches a 8.8 k value (t = 110 c), the voltage developed across its terminal is v otp . the internal comparator trips and latches ? off the part. reset occurs in similar conditions as described in the ovp section. ? short ? circuit protection: short ? circuit and especially over ? load protection are difficult to implement when a strong leakage inductance between auxiliary and power
dap018a/b/c/d/f http://onsemi.com 14 windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8 v maximum peak current limit is activated, an error flag, ipflag, is asserted and a time period starts, thanks to an adjustable timer. if the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latch ? off phase, operating in a low ? frequency burst ? mode. to limit the fault output power, a divide ? by ? two circuitry is installed on the v cc pin and requires twice a start ? up sequence before another attempt to re ? start is. as soon as the fault disappears, the smps resumes operation. the latch ? off phase can also be initiated, more classically, when v cc drops below v cc(min) (7.9 v typical). start ? up sequence when the power supply is first connected to the mains outlet, the internal current source is biased and charges up the v cc capacitor. when the voltage on this v cc capacitor reaches the v cc(on) level (typically 15 v), the current source turns off, reducing the amount of power being dissipated. at this time, the v cc capacitor only supplies the controller, and the auxiliary supply should take over before v cc collapses below v cc(min) . figure 32 shows the internal arrangement of this structure: figure 32. the current source brings v cc above 15 v (typical) and then turns off - + + + 14 10 8 ic1 or 0 v cc(on) v cclatch hv in some fault situations, a short ? circuit can purposely occur between v cc and ground. in high line conditions (v hv = 370 vdc) the current delivered by the startup device will seriously increase the junction temperature. for instance, since ic1 equals 2 ma (the min corresponds to the highest t j ), the device would dissipate 370 x 2m = 740 mw. to avoid this situation, the controller includes a novel circuitry made of two startup levels, ic1 and ic2. at power ? up, as long as v cc is below a certain level (1.8 v typ.), the source delivers ic1 (around 500 a typical), then, when v cc reaches 1.8 v, the source smoothly transitions to ic2 and delivers its nominal value. as a result, in case of short ? circuit between v cc and gnd, the power dissipation will drop to 370 x 500 = 185 mw. figure 33 portrays this particular behaviour: vth t1 t2 ic1 min ic2 min figure 33. the startup source now features a dual ? level startup current cv cc = 33 f v cc(on) v cc the first startup period is calculated by the formula c x v = i x t, which implies a 22 x 1.8 / 200 = 198 ms startup time for the first sequence. the second sequence is obtained by changing to 2 ma with a delta v of v cc(on) ? v th = 15 ? 1.8 = 13.2 v, which finally leads to a second startup time of 13.2 x 22 / 2m = 145 ms. the total startup time becomes 198 m + 140 m = 343 ms with a worst case condition on the startup source only. please note that this calculation is approximated by the presence of the knee in the vicinity of the transition. as soon as v cc reaches v cc(on) , drive pulses are delivered on pin 9 and the auxiliary winding increases the voltage on the v cc pin. because the output voltage is below the target (the smps is starting up), the controller smoothly ramps up the peak current to i p,max (0.8 v / r sense ) which is reached after a typical soft ? start period. this soft ? start period is internally fixed and lasts typically 5 ms. as soon as the peak current setpoint reaches its maximum (during the startup period but also anytime an overload occurs), an internal error flag is asserted, ipflag, indicating that the system has reached its maximum current limit set point (i p = i p,max ). as soon as the error flag gets asserted, the current source on pin 3 is activated and charges up the capacitor connected to this pin. if the error flag is still asserted when the timer capacitor has reached the threshold level v tim fault, (which is about 100 ms with a 0.22 f typically), then the controller assumes that the power supply has really undergone a fault condition and immediately stops all pulses to enter a safe burst operation. figure 34 depicts the v cc evolution during a proper startup sequence, showing the state of the internal error flag:
dap018a/b/c/d/f http://onsemi.com 15 ss = 5 ms current setpoint ipflag 100ms timer full power freq. foldback / skip level regulation no error has been confirmed user powers up! feedback loops reacts... figure 34. an error flag gets asserted v cc(on) v cc(min) v cc v fb i p,max v cclatch v ccreset an error flag gets asserted as soon as the current setpoint reaches its upper limit (0.8 v/r sense ). here the timer lasts 100 ms, a 0.22 f capacitor being connected to pin 3. short ? circuit or overload mode there can be various events that force a fault on the primary side controller. we can split them in different situation, each having a particular configuration: 1. the converter regulates but the auxiliary winding collapses: this is a typical situation linked to the usage of a constant ? current / constant ? voltage (cc ? cv) type of secondary ? side controller. if the output current increases, the voltage feedback loop gives up and the current loop takes over. it means that vout goes low but the feedback loop is still closed because of the output current monitoring. therefore, seen from the primary side, there is no fault. however, there are numerous charger applications where the output voltage shall not go below a certain limit, even if the current is controlled. to cope with this situation, the controller features a precise under ? voltage lockout comparator biased to a v cc(min) level. when this level is crossed, whatever the other pin conditions, pulses are stopped and the controller enters the safe hiccup mode, trying to re ? start. figure 35 shows how the converter will behave in this situation. if the fault goes away, the smps resumes operation.
dap018a/b/c/d/f http://onsemi.com 16 ipflag timer drv regulation duration given by aux. cap. current loop action keeps fb ok (cc operation) can be very slow... < 100ms < 100ms figure 35. first fault mode case v cc v fb v cclatch v ccreset v cc(on) v cc(min) first fault mode case, the auxiliary winding collapses but feedback is still there (0.22 f timer capacitor) 2. in the second case, the converter operates in regulation, but the output is severely overloaded. however, due to the bad coupling between the power and the auxiliary windings, the controller v cc does not go low. the peak current is pushed to the maximum and the timer starts to count. upon completion, all pulses are stopped and dual ? startup hiccup mode is entered. if the fault goes away, the smps resumes operation.
dap018a/b/c/d/f http://onsemi.com 17 timer < 100ms drv 100ms duration given by timer reg. 100ms ipflag figure 36. this case is similar to a short ? circuit where v aux does not collapse v fb v cc v cc(on) v cc(min) v ccreset v cclatch v out is overloaded (aux is alive) 3. a third case exists where the short ? circuit makes the auxiliary level go below v cc(min) . in that case, the timer length is truncated and all pulses are stopped. the double hiccup fault mode is entered and the smps tries to re ? start. when the fault is removed, the smps resumes operation. timer drv reg. duration given by aux. cap. < 100ms < 100ms ipflag figure 37. this case is similar to a short ? circuit where v aux does collapse v fb v cc v cc(on) v cc(min) v ccreset v cclatch v out is shorted (aux is gone)
dap018a/b/c/d/f http://onsemi.com 18 the recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the v cc capacitor. figure 38 details the various time portion a hiccup is made of: drv timer timer figure 38. the burst period is ensured by the v cc capacitor charge / discharge cycle (here a 0.22 f capacitor on timer) v cc v cclatch v ccreset t 1 t 2 t 1 t 3 t 2 v cc(on) v cc(min) if by design we have selected a 22 f v cc capacitor, it becomes easy to evaluate the burst period and its duty ? cycle. this can be done by properly identifying all time events on figure 38 and applying the classical formula: t c v i ? t 1 : i = icc3 = 600 a, v = 9 ? 6.5 = 2.5 v t 1 = 91 ms ? t 2 : i = 3 ma, v = 15 ? 6.5 = 8.5 v t 1 = 62 ms ? t 3 : i = 600 a, v = 15 ? 6.5 = 8.5 v t 1 = 311 ms ? t 1 = t 1 = 91 ms ? t 2 = t 2 = 62 ms the total period duration is thus the sum of all these events which leads to t fault = 617 ms. if the timer lasts 100 ms, then our duty ? cycle in auto ? recovery burst equals 100/(617 + 100) 13%, which is good. should the user like to further decrease or, to the contrary, increase this duty ? cycle, changing the v cc capacitor is an easy job. latch ? off and over voltage protection speedking ii features a fast comparator that permanently monitors pin 2 level. figure 39 details how it is internally arranged: figure 39. a comparator monitors pin 2 and latches ? off the part in case the threshold is reached rupper - + rlower 10 nf c1 2 vlatch + vccaux + 20 s time constant aux. s r q q latched fault 5 v reset
dap018a/b/c/d/f http://onsemi.com 19 figure 40. the part is reset when v cc reaches 5 v or when bo senses the bulk capacitor voltage is back to normal the user has unplugged, reset! fault! v latch v latch drv v cc(on) v cc(min) v ccreset v cclatch v cc(min) v cc(on) v cc if for any reason the latch pin level grows above v latch , the part immediately stops pulsing and stays latched in this position until the user cycles down the power supply. the reset actually occurs if v cc drops below 5 v, e.g. if the adapter user disconnects it from the mains. figure 40 details the operating diagrams in case of a fault. please note the presence of rc time constant on the comparator output, aimed to filtering any spurious oscillations linked to an eventual noise presence. the typical value of this time constant is 20 s. on both ovp and otp events and in the case of a latched ? ocp version, the latch reset occurs in the following conditions: ? a user reset via a mains interruption (unplug and replug adapter) which is long enough to let the v cc capacitor discharge to the controller reset level of 5 v. ? for b & d versions, a reset can occur if the brown ? out circuitry is asserted before the v cc reaches 5 v. soft ? start the speedking ii features an internal soft ? start circuit activated during the power on sequence (pon) but also in fault recovery (short ? circuit protection or brown ? out release). as soon as v cc reaches v cc(on) , the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 0.8 v/r sense ). the peak current is clamped at 0.8 v/r sense through the entire soft ? start period until the supply enters regulation. figure 41 shows a typical startup shot. vss vcc 8.56m 9.23m 9.90m 10.6m 11.2m ? 300m 100m 500m 900m 1.30 plot1 1 7.95m 8.95m 9.95m 10.9m 11.9m time in seconds 9.00 10.0 11.0 12.0 13.0 plot2 2 vss vcc ? 300m 100m 500m 900m 1.30 vss in volts 1 9.00 10.0 11.0 12.0 13.0 vcc in volts 2 figure 41. soft ? start is activated during a start ? up sequence, an auto ? recovery burst ? mode or when the brown ? out pin is released 5 ms v cc(on) v cc i p (t)
dap018a/b/c/d/f http://onsemi.com 20 the soft ? start is activated in the following conditions: ? startup sequence: when the user powers the adapter, the peak current smoothly ramps ? up from a low value towards a maximum value defined by the sense resistor. ? in auto ? recovery burst ? mode (e.g. during a non ? latched short ? circuit), each new set of pulses starts with a soft ? start sequence. ? when the brown ? out pin senses a reset on the bulk voltage, the controller restarts via a soft ? start sequence, just like a fresh power ? on sequence. * please note that speedking ii does use implement the soft ? burst technique as built in the original speedking circuit. internal ramp compensation ramp compensation is a known mean to cure subharmonic oscillations. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ? cycle greater than 50%. to lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. figure 42 depicts how internally the ramp is generated. * please note that the ramp signal will be disconnected from the cs pin, during the off time. figure 42. inserting a resistor + - from fb setpoint l.e.b. latch reset 20 k rcomp rsense cs on 1.8 v 0 v inserting a resistor in series with the current sense information brings ramp compensation and stabilizes the converter in ccm operation. in the speedking ii controller, the oscillator ramp features a 1.8 v swing. if our clock operates at a 65 khz frequency, then the oscillator slope corresponds to a 120 mv/ s ramp. in our flyback design, let?s assume that our primary inductance l p is 350 h, and the smps delivers 12 v with a n p :n s ratio of 1:0.1. the off ? time primary current slope is thus given by: v out v f n s n p l p 371 ma sor37mv s when projected over a sense resistor r sense of 0.1 , for instance. if we select 75% of the downslope as the required amount of ramp compensation, then we shall inject 27 mv/ s. our internal compensation being of 120 mv/ s, the divider ratio (divratio) between r comp and the 20 k is 0.225. r comp can therefore be obtained using the following value: r comp r ramp divratio (1
divratio) 20 k 0.225 1
0.225 5.8 k brown ? out protection versions b and d of the controller include a dedicated circuitry which permanently monitors the bulk capacitor level. figure 43 depicts the comparator arrangement known as a brown ? out protection: + ? vbo 1v ibo rupper 3.3meg rlower 10k bo brown out bulk figure 43. a brown ? out circuit protects the power supply against low input voltages 10
dap018a/b/c/d/f http://onsemi.com 21 when the input voltage is low, below v bo(on) , the bo comparator output is low and the current source is activated, drawing 10 a from the bo pin (pin 11) to ground. the controller is silent, and no driving pulses are delivered to the power mosfet. when the input is suf ficiently high, the bo comparator toggles high and shuts down the current source, providing the necessary hysteresis to the circuit. when toggling high, the bo signal also resets all the internal logic circuits including an eventual latch state triggered by an ovp for instance (or a latched ocp for this particular version). when the bo comparator has given the authorization to work, the controller resets its hiccup mode on the v cc (if any) and waits for the next v cc(on) event to start pulsing again (via soft ? start sequence). a 20 s rc time ? constant has been added in series with the brown ? out comparator to further avoid false trigger of the controller. figure 44 shows typical signals in presence of a brown ? out suddenly occuring and coming back again: bo signal drv 1 restart bo acknowledged here: hiccup reset general internal reset (latch...) double hiccup mains figure 44. a brown ? out event immediately stops the driving pulses v bo(off) v bo(on) interruption controller waits for the next v cc(on) event v bulk v ccreset v cclatch v cc(min) v cc(on) v cc when the bulk comes back to its normal level, the controller waits for the next v cc(on) event to re ? start pulsing. if the controller was in a double ? hiccup mode, the logic circuit is reset to accelerate the restart to the next v cc(on) event.
dap018a/b/c/d/f http://onsemi.com 22 bo signal restart mains interruption the bo information is latched. the next re ? start drv figure 45. a brown ? out event immediately stops the driving pulses occurs when v cc hits v cc(on) again v bo(on) v bo(off) controller waits for the next v cc(on) event (fresh re ? start) v bulk v ccreset v cclatch v cc(min) v cc(on) v cc when the bulk comes back to its normal level, the controller waits for the next v cc(on) event to re ? start pulsing. in this case, the bo re ? appears while v cc was still ok but the controller waits for v cc to ramp down to v cclatch then performs a fresh re ? start before pulsing again. the bridge resistors can be evaluated using the following equations: r upper v bo,on
v bo,off i bo (eq. 1) r lower v bo r upper v bo,off
v bo (eq. 2) where v bo = 1 v typical and i bo = 10 a typical. suppose the adapter designer needs a turn ? on voltage of 100 vdc and a turn ? off voltage of 50 vdc, then the upper resistor would be 4.9 m and the lower side resistor 100 k . the total dissipation for a 330 vdc bulk rail would amount to 22 mw. * please note that the current source arrangement brings un ? precision to the turn ? on voltage only, whereas the turn ? off voltage is only dependent on the v bo reference voltage. frequency foldback and skip cycle unlike its predecessor, speedking ii implements a frequency reduction in low power mode. also called frequency foldback, this technique has proven to offer a good performance, especially in the middle of the power range. on this controller, the foldback occurs when the peak current reaches a level set via the original skip pin (pin 5). once the peak current reaches this value, via a decrease in the feedback voltage, the controller freezes it and the only way to further reduce the output power is to fold the frequency back. the frequency variation is ensured over a delta feedback voltage of around 500 mv. when the frequency hits the frequency limit ( f trans ), the frequency reduction is stopped. at this point, if the load goes further down, the feedback voltage drops and when it reaches 300 mv, the controller enters traditional skip ? cycle (no soft ? burst). at full power, the peak current varies according to the power demand, the switching frequency being fixed to 65 khz. the feedback voltage is allowed to move between 300 mv and 3.4 v which is the upper feedback limit beyond which a fault is detected. when the load starts to decrease, the feedback voltage goes down to impose lower peak
dap018a/b/c/d/f http://onsemi.com 23 currents. when the feedback pin reaches the v fold level, the peak current is set to v fold /4.2 and cannot decrease anymore. the feedback voltage continues to go down but it now changes the switching frequency down to 26 khz (typical), naturally reducing the amount of transmitted power. when the feedback touches a typical 300 mv limit, skip ? cycle takes place. the whole behavior is illustrated by figure 46: figure 46. the controller changes its operating frequency in light load conditions further details are given by figure 47 which represents both switching frequency and peak current setpoints in relationship to the feedback voltage. pin 5 provides a means to alter the foldback limit. to fine tune the ef ficiency but also to combine a low skip current level and a reduced acoustic noise in standby, the designer must wire a resistor to ground to set the foldback level (figure 48). as we internally have a 10 a current source, the relationship is straightforward: r fold v fold 10 (eq. 3) for instance, suppose we want to set the folback point to 1 v, then the resistor value should be 100 k . we recommend to put a 10 nf capacitor to ground on this pin. both the resistor and the capacitor must be placed very close to the controller to avoid any noise pick ? up. because the clock frequency must reach 26 khz at a feedback voltage of 300 mv, pin 5 level cannot be set too low in order to provide enough dynamic range for the voltage ? controlled oscillator (vco). to obtain a good linearity, we recommend a minimum voltage dynamics of 300 mv, which implies a level on pin 5 always above 600 mv. also, setting the frequency foldback too low will alter the performance in standby power. the graphs in figure 47 (65 khz version) depict the operation in light load conditions where the frequency is decreased down to 26 khz (typical) figure 47. operation in light load conditions
dap018a/b/c/d/f http://onsemi.com 24 figure 48. a pulldown resistor adjusts the foldback level foldback circuitry - + rload vfold 5 6 7 / 4.2 / 4.2 + - leb 0.8 v c1 10 nf v dd ifold 10 clock 300 mv skip cycle comparator current sense comparator reset this point cannot be lower than vfold / 4.2 bias reduction in light load when the power supply enters deep standby mode (skip ? cycle is active), a comparator instructs the controller that it entered in light load conditions. when this happens, the circuit reduces various internal bias currents to further bring its consumption down and improve the consumption in no ? load conditions. frequency jittering frequency jittering is a method used to soften the emi signature by spreading the energy in the vicinity of the main switching component. speedking ii offers a 5% deviation of the nominal switching frequency. the sweep sawtooth is internally generated and modulates the clock up and down with an adjustable period. figure 49 displays the internal arrangement around pin 4. it is actually a i ? 2i generator, producing a clean 50% duty ? cycle sawtooth. if we take a 2 v swing on the jitter capacitor, then we calculate the needed value for a 4 ms period, or a 250 hz modulation speed, again applying the v x c = i x t relationship. we need 2 ms to ramp ? up and 2 ms to ramp down, therefore: c = 20 x 2 m / 2 = 20 nf. if we select a 22 nf , then our modulation frequency will be around 227 hz... figure 50 shows the relationship between the jitter ramp and the frequency deviation. figure 49. an internal ramp is used to introduce frequency jittering on the oscillator sawtooth - + + frequency modulation to clock circuit ctimer 4 jitter v dd vcjitp vcjitv icjit 2.icjit
dap018a/b/c/d/f http://onsemi.com 25 65khz 68.9khz 61.1khz adjustable figure 50. modulation effects on the clock signal by the jittering sawtooth jitter ramp internal sawtooth over power protection there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip ? cycle disturbance brought by the current ? sense offset. a way to reduce the power capability at high line is described by figure 52. on this drawing, a voltage is derived from the auxiliary winding and produces a negative level during the on ? time of the main power transistor. the negative voltage amplitude directly relates to the input level via the transformer turn ratio linking the primary winding to the auxiliary winding. figure 51 depicts the typical signal obtained on the auxiliary winding: 1 v(24) 464u 472u 480u 488u 496u time in seconds ? 40.0 ? 20.0 0 20.0 40.0 v(24) in volts plot1 1 1 ? 40.0 ? 20.0 0 20.0 40.0 1 figure 51. the signal obtained on the auxiliary winding swings negative during the on ? time off ? time on ? time n 1 (v out + v f ) ? n 2 v bulk during the off ? time, the voltage plateaus to a positive level depending on the turn ratio between the output winding (n s ) and the power winding. this ratio is noted n 1 . during the on ? time, the transformer terminal swings to a negative voltage whose amplitude now depends on the turn ratio n 2 , equal to the primary (n p ) to the auxiliary winding ratio (n aux ). if we place a resistive divider between the auxiliary winding and the opp pin, as suggested by figure 52, we have a means to influence the internal setpoint as the bulk voltage increases. the equations to design the network are fairly simple: suppose we need to reduce the peak current from 2.5 a at low line, to 2 a at high line. this corresponds to 20% reduction or a setpoint voltage of 640 mv. to reach this level, then the negative voltage developed on the opp pin must reach: v opp 800
640 ? 160 mv (eq. 4)
dap018a/b/c/d/f http://onsemi.com 26 figure 52. the opp circuitry affects the maximum peak current setpoint by summing a negative voltage to the internal voltage reference opp roppu this point will be adjusted to reduce the ref at hi line to the desired level. iopp roppl v dd + - cs reset from fb ref + v cc aux 0.8 v 5% ref = 0.8 v + vopp (vopp is negative) sum2 k1 k2 swings to: n1vout during t off ? n2vin during t on let us assume that we have the following converter characteristics: v out = 19 v v in = 85 to 265 vrms n 1 = n p :n s = 1:0.2 n 2 = n p :n aux = 1:0.16 given the turn ratio between the primary and the auxiliary windings, the on ? time voltage at high line (265 vac) on the auxiliary winding swings down to: v aux ? n 2 v in,max ? 0.16 375 ? 60 v (eq. 5) to obtain a level as imposed by equation 3, we need to install a divider featuring the following ratio: div 0.16 60 0.00266 (eq. 6) if we arbitrarily fix the pulldown resistor r oppl to 1 k , then the upper resistor can be obtained by: r oppu 60
0.16 0.16 1k 374 k (eq. 7) if we now plot the peak current setpoint obtained by implementing the recommended resistor values, we obtain the following curve: 100% 20% peak currentsetpoint v bulk 375 100% 20% v bulk 375 figure 53. the peak current regularly reduces down to 20% at 375 vdc the opp pin is made of zener diodes arranged to protect the pin against esd pulses. these diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. on the other side, negative injection into these diodes (or forward bias) can cause substrate injection wich can lead to an erratic circuit behaviour. to avoid this problem, the pin is internall clamped slightly below ?300 mv which means that if more current is injected before reaching the esr forward drop, then the maximum peak reduction is kept to 40%. if the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond ?2 ma. given the value of r oppu , there is no risk in the present example. on figure 53, we can see that the opp starts to fold the setpoint immediately from a low mains operation. this is no different than a standard opp circuitry built from a resistive string placed between the bulk rail and the current sense pin. however, in some applications, it is good to remove the opp at low line and place a small threshold so that our opp only changes the circuit power capability at high line only. figure 54 offers a possible solution built on a zener diode connection.
dap018a/b/c/d/f http://onsemi.com 27 figure 54. the zener diode can introduce a threshold which disables opp at low line for maximum power capability opp roppu this point will be adjusted to reduce the ref at hi line to the desired level. iopp roppl v dd + - cs reset from fb ref + v cc aux 0.8 v 5% ref = 0.8 v + vopp (vopp is negative) sum2 k1 k2 rbias dz swings to: n1vout during t off ? n2vout during t on suppose we need a threshold placed at 150 vdc. in that case, give the turn ratio, we need to install a zener diode featuring the following breakdown voltage: v z 150 0.16 24 v (eq. 8) in high line conditions (v bulk = 375 vdc), the voltage on the zener diode voltage will now swing to: v aux ? n 2 v in,max 24 ? 0.16 375 24 ? 36 v (eq. 9) applying equation 6 again, we have: r oppu 36
0.16 0.16 1k 224 k (eq. 10) the new compensation now looks like what figure 55 shows: 100% 20% peak current setpoint v bulk 375 150 100% 20% peak current setpoint v bulk 375 150 figure 55. the addition of the zener diode introduces a threshold at 150 vdc the bias resistor r bias , makes sure that enough current circulates in the zener diode to make it work far enough from its knee. the tradeoff includes the power consumption brought by the addition of this new component. further reduction can be obtained by inserting a standard diode in series with the zener to block the positive excursion.
dap018a/b/c/d/f http://onsemi.com 28 package dimensions soic ? 14 d suffix case 751a ? 03 issue h notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint 7x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. dap018/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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